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LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
DESCRIPTION
KEY FEATURES High Current Biphase Operation Outputs As Low As 0.800V Biphase LoadSHARETM Transient Correction LoopTM Reduces Required Capacitance Differential Amplifier For Remote Voltage Sensing Integrated High Current MOSFET Drivers 200KHz to 1MHz Frequency Operation Programmable Slew Rate Control For Start-Up Sequence and VID change VID Changes On The Fly Power Good Indicator Short Circuit Protection Output Over Voltage and Under Voltage Protection No current-sense resistors
APPLICATIONS
The LX1677 is a highly integrated VRM power supply controller IC featuring two PWM switching regulator stages. The two constant frequency voltage-mode PWM phases are configured as a single biphase high current output core supply. In biphase operation, the high current (>35A) output is generated by a LoadSHARETM technique that balances the currents in the two phases. Power loss and noise, due to the ESR of the input capacitors, are minimized by operating the PWMs 180 out of phase. A synchronized Transient Correction Loop provides exceptional control of the output droop and overshoot during very high di/dt load changes, the circuit can be configured for droop only, overshoot only or both. This architecture also minimizes capacitor requirements while
maximizing regulator response. A true differential input amplifier is used for remote voltage sensing at the processor core. A VID code generator provides an internal reference that will set the output voltage. This VID code can be changed during operation and the reference will slew the output voltage to its new setting at a preset rate. During VID changes on the fly the Power Good indication will stay valid. The current through the lower phase 1 MOSFET will be sampled using its RDS(ON) for current limit and shut down. For further protection, an over voltage circuit will trip at a specified setting and clamp the output by turning off the upper MOSFETs and turning on the lower MOSFETs. The upper MOSFET drivers use a bootstrap capacitor to provide the upper drive voltage over the input voltage range of 6 to 24 volts.
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IMPORTANT: For the most current data, consult MICROSEMI's website: http://www.microsemi.com Protected By US Patents: US6292378,US6285571 Protected By US Patents: US6825571, US6356063, US6605931
AMD Athlon 64TM and AMD OpteronTM Processors Processor Core Voltage Supply Voltage Regulator Modules
PRODUCT HIGHLIGHT
T r a n s ie n t C o r e c tio n L o o p V in + 5 V V in 6 to 2 4 V
70nH
5 B it V ID
LX1677
V in 6 to 2 4 V Vout
LX1677 LX1677
PACKAGE ORDER INFO
TJ (C) 0 to 70
PW
Plastic TSSOP 38-Pin LX1677CPW
LQ
Plastic MLPQ 38-Pin LX1677CLQ
RoHS Compliant / Pb-free Transition DC: 0518
RoHS Compliant / Pb-free Transition DC: 0512
Note: Available in Tape & Reel. Append the letters "TR" to the part number. (i.e. LX1677CLQ-TR)
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
ABSOLUTE MAXIMUM RATINGS
PACKAGE PIN OUT
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Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. x denotes respective pin designator 1, 2, or 3
THERMAL DATA
LQ
Plastic MLPQ 38-Pin 8C/W 35C/W
THERMAL RESISTANCE-JUNCTION TO CASE, JC THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA
PW
Plastic TSSOP 38-Pin 12.2C/W 38C/W
THERMAL RESISTANCE-JUNCTION TO CASE, JC THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA
EA2EO2 FB+ FBDFOUT EO1 EA1DACOUT PWGD GND VIN ROSC ENA VID4 VID3 VID2 VID1 VID0 VS2
1
VID2 VID1 VID0 VS2 HO2 VC2 VCC
Supply Input Voltage (VCCL, VCC)................................................-0.3V to 6.0V Battery Input Voltage (VIN) ..............................................................-0.3V to 24V Current Limit Sense (ILIM1, ILIM3) ................................................-0.3V to 30V Topside Driver Supply Input Voltage (VC1, VC2, VC3)........ -0.3 to VSx + 6.0V Topside Driver Return Input Voltage (VS1, VS2)................................-5V to 24V Differential Sense Input Voltage (FB+, FB-)....................................-0.3V to 6.0V VID0 - VID4, Input Voltage ...............................................................-0.3V to 6V High Side Driver Peak (<500ns) Current (HO1/2, I-MAX) ............................+1A Low Side Driver Peak (<500ns) Sink Current (LO1/2, I-MIN)....................+1.5A Operating Junction Temperature.................................................................. 150C Storage Temperature Range...........................................................-65C to 150C Lead Temperature (Soldering 10 seconds) .................................................. 300C RoHS Peak Package Solder Reflow Temperature (40 second maximum exposure) ..................................................... 260C (+0, -5)
FB+ EO2 EA2LP2 LP1 ILIM1
FBDFOUT EO1 EA1DACOUT PWGD GND VIN ROSC ENA VID4 VID3
1 2 3 4 5 6 7 8 9 10 11 12
38
37 36
35
34
33
32
ILIM3
31 30 29 28 27
Connect Bottom to Power GND
26 25 24 23 22 21
13
14
15
16
17
18
19
20
VS3 I-MAX VC3 VC1 HO1 VS1 LO1 PGN LO2 VCCL I-MIN PGN3
LQ PACKAGE
(Top View)
38
19
20
(Top View)
LP2 LP1 ILIM1 ILIM3 VS3 I-MAX VC3 VC1 HO1 VS1 LO1 PGN LO2 VCCL I-MIN PGN3 VCC VC2 HO2
PW PACKAGE RoHS / Pb-free 100% Matte Tin Lead Finish
Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow.
RECOMMENDED OPERATING CONDITIONS Parameter IC Input Supply Voltage Battery Input Voltage Biphase Topside Driver Return Voltage Transient Correction Phase Driver Return Voltage Symbol VCC VIN VS1, VS2 VS3 LX1677 Typ Units V V V V
Min 4.5 5.7 0 0
Max 5.5 24.0 24.0 5.5
PACKAGE DATA PACKAGE DATA
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
FUNCTIONAL PIN DESCRIPTION Name FB+ FBDFOUT EA1EO1 GND ROSC ENA DACOUT VID4 VID3 VID2 VID1 VID0 PWGD VCC VC3 PGN3 I-MIN VS3 I-MAX ILIM3 LP1 EA2EO2 LP2 VIN LO2 VS2 HO2 VC2 PGN LO1 ILIM1 VS1 HO1 VC1 VCCL Description Differential Amplifier Positive Input - Feedback from output Differential Amplifier Negative Input - Feedback from output Differential Amplifier Output Phase 1 Error Amplifier Negative Input Phase 1 Error Amplifier Output Analog Ground A resister to ground sets PWM frequency Enable Input - Logic Low disables all converter phases DAC Output voltage - 50uA bi-directional current source Digital Input for VID code - Has an internal pull-up resister Digital Input for VID code - Has an internal pull-up resister Digital Input for VID code - Has an internal pull-up resister Digital Input for VID code - Has an internal pull-up resister Digital Input for VID code - Has an internal pull-up resister Power Good Output Pin - Open drain output pin for power good indication. High = Power Good IC Supply Voltage. Nominal +5V Supply for transient correction phase upper MOSFET driver, bootstrap voltage Power ground pin for Transient Correction Loop driver Output Driver for lower Transient Correction Loop MOSFET Low side of upper driver for Transient Correction Loop - MOSFET Driver power return Output Driver for upper Transient Correction Loop MOSFET Transient Correction Loop current sense - A resister sets an upper limit for over current detection and shut down. Phase 2 differential amplifier positive input, filtered feedback from phase 1 output Negative Input of phase 2 integrating amplifier Output of phase 2 integrating amplifier Phase 2 differential amplifier negative input, filtered feedback from phase 2 output Battery Voltage Input. Driver Output for phase 2 lower MOSFET Low side of upper gate driver for phase 2. Driver Output for phase 2 upper MOSFET Supply for phase 2 upper MOSFET driver, bootstrap voltage Power ground pin for current sensing of lower MOSFET RDS(ON) for phase 1.
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PACKAGE DATA PACKAGE DATA
Driver Output for phase 1 lower MOSFET Over-Current Limit Set - A resister sets an upper limit for over current detection and shut down. Low side of upper gate driver for phase #1. Driver Output for phase 1 upper MOSFET Supply for phase 1 upper MOSFET driver, bootstrap voltage Voltage bus for the lower MOSFET drivers. Nominal +5V
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS Unless otherwise specified, the following specifications apply over the operating ambient temperature 0C TA 70C except where otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VIN = 12V, Switching Frequency = 500KHz. Parameter
REGULATOR
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Symbol
Test Conditions ENA = VCC, FB+ = FBENA = GND ENA = VCC, FB+ = FBENA = VCC, FB+ = FBCommon Mode Voltage (VCM) = 1.4V
Min 1
LX1677 Typ 5 0.5 2
Max 9 1 1 4 6 100
Units mA A mA mA mV nA dB V V MHz
IC Supply Current Low Side Driver Operating Current High Side Driver Operating Current
ERROR AMPLIFIER: PHASE 1
IQ(VCC) IQ(VCCL) IQ(VCx) VOS IEA1 VICM VEO1(MAX) VEO1(MIN) UGBW VOS ADA CMRRDA RIN VCM VDFOUT(MAX) VDFOUT (MIN) UGBW SR fMAX fMIN
Input Offset Voltage Input Bias Current DC Open Loop Gain Input Common Mode Range Output Voltage Swing Unity Gain Bandwidth
DIFFERENTIAL AMPLIFIER
CMRR > 50dB IEA1 = 2mA IEA1 = -20A
-6 -100 60 0.8
70 2.5 4.0 0.15 20 0.5
Input Offset Voltage Gain Common Mode Rejection Ratio Input Resistance Input Common Mode Range Source / Sink Current Output Voltage Swing Unity Gain Bandwidth Slew Rate
OSCILLATOR
VCM=1.4V 0.8V < VCM < 2.5V Measured at FB+ Input
-6 0.99
1 65 30 5 4.0 0.2 10 5
6 1.01
0 VDFOUT = 0V IDFOUT = 2mA IEA1 = -20A
3
mV V/V dB K V mA V MHz V/s
Maximum Clock Frequency Minimum Clock Frequency Frequency Stability
PWM OUTPUT
RPWM=10k RPWM=50k
0.9 150
1 200 4
1.1 220
MHz KHz % % nS nS V
Maximum Duty Cycle Minimum Pulse Width Dead Time Ramp Amplitude
PHASE 2 INTEGRATING AMPLIFIER
DCMAX tPWM(MIN)
VRAMP
During Transient Correction Switching Transient Correction Not Switching 3000pF Load 3000pF Load at 50% of VCCL VIN = 6V VIN = 12 VIN = 24V VCM=1.4V IEA2 = 2mA IEA2 = -20A
40 50 60 80 0.70 1.40 2.80
100 50 200
ELECTRICALS ELECTRICALS
Input Offset Voltage DC Open Loop Gain Output Voltage Swing Unity Gain Bandwidth
VOS VEO2(MAX) VEO2(MIN) UGBW
-6 70 4.0 0.15 20
6
mV dB V MHz
0.5
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS (CONT) Unless otherwise specified, the following specifications apply over the operating ambient temperature 0C TA 70C except where otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VIN = 12V, Switching Frequency = 500KHz. Parameter
PHASE 2 DIFFERENTIAL AMPLIFIER
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Symbol VOS ADA CMRRDA RB UGBW LP1=LP2
Test Conditions
Min -6 0.98
LX1677 Typ
Max 6 1.02
Units mV V/V dB K MHz
Input Offset Voltage Gain Common Mode Rejection Ratio Input Resistance Unity Gain Bandwidth
TRANSIENT CONTROL LOOP
Common Mode Voltage = 0 to 2 V
1 60 180 4
Voltage Droop Sense Propagation Delay : FB+ and FB- to I-MAX Voltage Overshoot Sense Propagation Delay : FB+ and FB- to I-MIN Voltage Droop Sense Threshold Voltage Overshoot Sense Threshold
OUTPUT DRIVERS
50
nS
50 VDFOUT Rising 3000pF Load VDFOUT Falling 3000pF Load 40 40
nS mV mV
Driver Rise Time Fall Time High Side Driver Voltage: [VHOx - VVSx] Drive High Drive Low Low Side Driver Voltage: [VLOx - VPGN] Drive High Drive Low High Side Driver Current Lower MOSFET Driver Current Current Sense Bias Current Current Sense Delay Current Sense Bias Current Current Sense Delay Logic Low Threshold Hysteresis Pullup Resistance
POWER GOOD
tRISE tFALL
CL = 3000pF, VCx - VSx = 5V
50 50
nS
VHOx = 20mA, VCx - VSx = 5.0 V VHOx = -20mA, VCx - VSx = 5.0 V
4.8
4.9 0.1
V 0.2 V 0.2
A A
IHOx ILOx
VLOx = 20mA, VCCL - VPGN = 5.0 V VLOx = -20mA, VCCL - VPGN = 5.0 V VCx - VSx = 5.0 V, Load = 3300pf at <500nSec VCCL - PGN = 5.0 V, Load = 3300pf at <500nSec
4.8
4.9 0.1
1 1.5
PHASE 1 OVER CURRENT PROTECTION
IILIM1 tCSD(ILIM1) IILIM3 tCSD(ILIM3)
44 200 40 200
50 400 50 400 1.5 0.3 100
60 500 60 500
A nS A nS
TRANSIENT CORRECTION LOOP OVER CURRENT PROTECTION
ENABLE INPUT / VOLTAGE IDENTIFICATION (VID)
E ELECTRICALS
V V K V
Low Output Voltage
VPWGD
IPWGD = -3mA
0.5
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS (CONT) Unless otherwise specified, the following specifications apply over the operating ambient temperature 0C TA 70C except where otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VIN = 12V, Switching Frequency = 500KHz. Parameter
UVLO
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Symbol
Test Conditions
Min
LX1677 Typ
Max
Units
VCC Threshold Hysteresis VIN Threshold Hysteresis
OVER VOLTAGE PROTECTION
VCC Rising
4.2 0.3 5.5 0.3 1.85 0.725
V
VIN Rising
Over Voltage Threshold
UNDER VOLTAGE PROTECTION
-
V V mV 1 2 %
Under Voltage Threshold
DAC
DAC Output Voltage Positioning Offset Initial DACOUT Accuracy
At No Load 1 VDACOUT 1.4 0.925 VDACOUT < 1
IHOx ILOx
-20 1.4 < VDACOUT 2
1 1.5 0.5 1.3 0.3 2
High Side Driver Current Lower MOSFET Driver Current VID Logic High Threshold VID Hysteresis
VCx - VSx = 5.0 V, Load = 3300pf at <500nSec VCCL - PGN = 5.0 V, Load = 3300pf at <500nSec
A A V V
VOLTAGE IDENTIFICATION (VID) CODE VID[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 VOUT (V) 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 VID[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VOUT (V) 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown
E ELECTRICALS
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
SIMPLIFIED BLOCK DIAGRAM
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DFOUT
EA1 -
EO1
I-MAX
VCCL
VC1
Diff Amp Phase 1 Error Amp
S 0
Q
HO1 R VS1
I-MIN
+
FB FB +
+
+
-
LO1
I-MIN
50A DAC VID0 VID1 VID2 VID3 VID4
2.35 DACOUT - 30mV POR I-MAX ILIM
PGOOD
+
DACOUT
180
R S
Q
PGN VC2 HO2 VS2 LO2
_
DACOUT 0.85
UV + _ OV + VCC UVLO VIN
SRS
Fault
S gm S S
Phase 2 Integrating Amp
100K 90K 90K
Bandgap
EO2
PWGD
PGOOD
DACOUT
VIN AMP FRQ OSC
PGN
+ _ VIN 0 180
VS3
35mV offset
IMAX
Phase 2 Differential Amp
ROSC
_IMIN + ENA VCCL
90K
35mV offset
_
VCC
Bandgap
GND
ILIM
ILIM
ILIM3 ILIM1
PGN3
I-Min
VS3 I-Max
VC3
ENA
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
+
+
+
-
EA2 LP1 LP2
90K
E ELECTRICALS
Page 7
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
APPLICATION CIRCUITS
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R2 61.9K C2 4700pF CR3 R3 61.9K C1 4700pF R8 100K R7 4.02K 2.00K R1 1N5817 C3 4700pF 6.04K R4 4.02K R5 38 37 35 34 U1 1 10K R19 NDS7002A Q8 C9 4700pF C26 0.22uF 2 3 4 NDS7002A Q7 5 6 7 C10 VBAT 10uF 25V R9 45.3K R10 1.00K 8 9 10 11 R11 100K R12 100K 13 14 15 16 17 18 19 R13 100K R14 100K R15 100K +5VP R6 10.0 C7 4.7uF 6.3V +5VP 12 36 33 32 C4 Q2 SI4842DY 31 30 29 CR4 28 C13 27 26 25 24 23 22 21 20 C24 4.7uF 6.3V C25 4.7uF 6.3V Q4 IRLR8203 C5 0.22 Q3 IRLR8203 Q10 N/U Q11 IRLR8203 VBAT C16 10uF 25V C22 10uF 25V 10uF 25V 1N5817 4.7uF 6.3V C28 +5VP 0.22 70nH CR2 SK32 +BATT IN C15 10uF 25V C36 10uF 25V VBAT Q1 SI4842DY CR1 SK32 +5 VIN C12 47uF 6.3V +5VP +5VP
C11 47uF 6.3V L3
+5 RTN
+5VP
EO2
LP2
EA2-
FB+
LP1
FBDFOUT EO1 EA1-
ILIM3
ILIM
VS3 I-MAX VC3 VC1 HO1
BATT RTN
DACOUT PWRGD GND VIN ROSC ENA VID4 VID2 VID1 VID0 VS2 VID3 VCC HO2 VC2 LX1677 LQ
VS1 LO1 PGN LO2 VCCL I-MIN PGN3
L1
2.2uH + C18 270uF 2V + C19 270uF 2V
VCORE RTN
C8 4.7uF 6.3V CR5
C29 +5VP C14 6.3V VBAT C17 10uF 25V 10uF 25V C23 10uF 25V
1N5817 R22 1.00K
4.7uF Q5 IRLR8203 C6 0.22 Q6 IRLR8203 Q13 IRLR8203 2.2uH + C20 270uF 2V + C21 270uF 2V Q12 N/U
L2
R23 1.00K
Enable VID 0 VID 0 VID 0 VID 0 VID 0 PWRGD VBAT C30 10uF 25V C31 10uF 25V C32 10uF 25V C33 10uF 25V VBAT C34 10uF 25V C35 10uF 25V
Figure 2 - Typical VRM Application
APPLICATIONS APPLICATIONS
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 8
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
THEORY OF OPERATION
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GENERAL DESCRIPTION The LX1677 is a voltage-mode pulse-width modulation controller integrated circuit. The PWM frequency is programmable from 200kHz to 1MHz. The device has external compensation, for more flexibility of the loop response. The LX1677 also makes use of a true differential input amplifier for remote voltage sensing at the actual processor core. This is a very important feature now that the core voltages are in the 1 to 2 volt range. The reference for the biphase PWM output is a 5 bit VID code DAC. The VID code DAC can generate a reference voltage of 0.925 to 2.000 volts. The output of the DAC is a bi-directional current source and is connected to the DACOUT pin. Connecting a capacitor from this pin to ground will generate a linear ramp, which will determine the rate of change of the output voltage. The rate of change can be set so that the current required to charge the total output capacitance is below the maximum current limit trip point. This will allow VID changes on the fly without tripping the over current sensor. POWER UP AND INITIALIZATION At power up, the LX1677 monitors the supply voltage to VCC and Vin, Before both supplies reach their undervoltage lock-out (UVLO) thresholds, a power on reset condition will prevent soft-start from beginning, the oscillator is disabled and all MOSFETs are kept off. SOFT-START Once the supplies are above the UVLO threshold and the Enable pin is brought high, the soft-start capacitor begins to be charged up by the reference DAC through the DACOUT pin. The capacitor voltage at the DACOUT pin rises as a linear ramp. The DACOUT pin is connected to the error amplifier's non-inverting input which controls the output voltage. The output voltage will follow the DACOUT pin voltage. Phase 3 (hysteretic phase) is disabled during soft-start. OVER-CURRENT PROTECTION There are two separate current limit circuits in the LX1677. One looks at the phase 1 lower MOSFET drain current and the second looks at the phase 3 upper MOSFET drain current. Both circuits have a 400 nS delay before a current limit command is issued to the current limit latch, once set the current limit latch will hold all three phases off until it is reset. The Over-Current Protection is disabled during positive VID changes.
To reset the current limit latch either the enable command (ENA) must be cycled low then back high or the input power must cycle off and then back on. OVER-CURRENT PROTECTION (PHASE 1) The phase 1 current limit uses the RDS(ON) of the lower MOSFET, together with a resistor (RSET) to set the actual current limit point. The current limit comparator senses the current 400 nS after the lower MOSFET is switched on. A current source supplies a current (ISET), of 50A which flows into RSET and determines the current limit trip point. The value of RSET is selected to set the current limit for the application. Phase 1 RSET is calculated by:
R SET = ILimit * RDS(ON) 50 A
The current limit comparator will trip when the drop across RSET equals the drop across the lower MOSFET RDS(ON)., at this time the comparator outputs a signal to set the I limit latch and removes the enable command. The Over-Current sensing is done on phase 1 only because phase 2 current is always being forced to equal the phase 1 current, therefore the current trip point is set at half of the desired current limit. For an output current limit setting of 30 amps, the current trip point for phase 1 is set at 15 amps. When the phase 1 over current latch is set all three phases are disabled, all MOSFETs are turned off.
Vin 50 uA Q1 RSET Vout
+ _ +
_
RDS(ON)
_ +
Iout
APPLICATIONS APPLICATIONS
Current Limit Comparator
Q2
Q2 Current Flow
400nSec Delay
Figure 3 - Phase 1 Current Limit
The delay before current limit is activated will result in current pulses exceeding the calculated values during the delay period if a short circuit is applied during that time.
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 9
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
THEORY OF OPERATION (CONTINUED)
WWW .Microsemi .C OM
OVER-CURRENT PROTECTION (PHASE 3) The hysteretic phase has its own current limit protection because with it's very fast response time with a 100 nH inductor the upper MOSFET cannot be allowed to stay on during an output short circuit condition. The phase 3 overcurrent sensing uses the RDS(ON) of the upper MOSFET with a resistor RSET to determine the over current limit point. A current source draws 50uA through RSET which determines the required drop across the MOSFET RDS(ON) to initiate a current limit condition.
50 uA RSET Vin
FAULT LOGIC There are a number of possible states that will cause a fault condition that will disable the output MOSFET drivers. A fault condition will be caused by the following: Enable (ENA) pin being pulled low Over-current condition on either phase 1 or phase 3 Over Voltage output > 1.85V Under Voltage output < 0.725V In all cases except Over Voltage all MOSFET drivers will be latched off. For an Over Voltage fault the lower MOSFETs for phase 1 and 2 will be held on to discharge the bulk capacitance on the output till a lower limit of 0.725 volts is reached then all MOSFETS will be turned off. To reset a fault it necessary to cycle the ENA pin low then back high or remove and reapply the input voltage VIN. The Under Voltage monitor is not enabled until the output voltage has ramped up to the level commanded by the DACOUT pin and the PWGD output in high. PWM FREQUENCY An external resistor sets the PWM frequency from the ROSC pin to ground. The equation for ROSC is:
ROSC =
ILIM3
_
+
+
RDS(ON)
+ _
Current Limit Comparator
VS3
Q1
_
Vout
400nS Delay Q2
Figure 4 - Phase 3 Current Limit
Phase 3 RSET is calculated by:
Rset = ILimit * RDSon 50uA
OVER VOLTAGE PROTECTION An over voltage protection circuit monitors the output voltage and will latch all three phases off if an over voltage condition (greater than 2.35 V) is detected. Both MOSFETs for phase 3 will be held off and the lower MOSFETs for phase 1 and 2 will be held on to discharge the output capacitor till the output voltage drops below .85 volt, at .85 volts all MOSFETs will be turned off.
(
1 K * f ) + 100e - 9
where ROSC is in , f is in Hz, K=105e-12
APPLICATIONS APPLICATIONS
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 10
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
THEORY OF OPERATION (CONTINUED)
THEORY OF OPERATION FOR A BI-PHASE, LOADSHARETM CONFIGURATION The basic principle used in LoadSHARETM in a multiple phase buck converter topology is that if multiple, identical, inductors have the same identical voltage impressed across their leads, they must then have the same identical current passing through them. The current that we would like to balance between inductors is mainly the DC component along with as much as possible the transient current. All inductors in a multiphase buck converter topology have their output side tied together at the output filter capacitors. Therefore this side of all the inductors has the same identical voltage. If the input side of the inductors can be forced to have the same equivalent DC potential on this lead, then they will have the same DC current flowing. To achieve this requirement, phase 1 will be the control phase that sets the output operating voltage, under normal PWM operation. To force the current of phase 2 to be equal to the current of phase 1; a second feedback loop is used. Phase 2 has a low pass filter connected from the input side of each inductor. This side of the inductors has a square wave signal that is proportional to its duty cycle. The output of each LPF is a DC (+ some AC) signal that is proportional to the magnitude and duty cycle of its respective inductor signal.
The second feedback loop will use the output of the phase 1 LPF as a reference signal for an error amplifier that will compare this reference to the output of the phase 2 LPF. This error signal will be amplified and used to control the PWM circuit of phase 2. Therefore, the duty cycle of phase 2 will be set so that the equivalent voltage potential will be forced across the phase 2 inductor as compared to the phase 1 inductor. This will force the current in the phase 2 inductor to follow and equal the phase 1 inductor current. With the LoadSHARETM topology it is possible to imbalance the phases so that one phase will supply more current than the other under unique situations. The LX1677 will normally be used with the same supply voltages on phase 1 and 2 PWM inputs and will have equal currents in both phases.
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Phase 1 Low Pass Filter Differential Feedbach From Vout
Phase 1 Diff Amp
Phase 1 Error Amp -
0
+ _
Phase 1 Comparator
PWM
HO1
DACOUT
+
LO1
LP1 +
DC Bias
DC Bias +
+
_ gm 180
Ramp .75 V to 3 V Both PWMs
PWM
HO2
Vout
DC Bias
-
Differential Amp
Phase 2 Integrating Amp
LP2 Phase 2 Low Pass Filter
EA -
EO2
Figure 5 - LoadSHARE Control Loop
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
-
+
Phase 2 Comparator
LO2
APPLICATIONS APPLICATIONS
Page 11
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
THEORY OF OPERATION (CONTINUED)
LOOP GAIN AUTOMATIC COMPENSATION The PWM ramp shown in Figure 5 is automatically adjusted to keep its amplitude a fixed percentage of Vin over the range of 6 to 24 V input. This maintains a constant loop gain that is set by the feedback networks around the error amplifiers independent of PWM input voltage. TRANSIENT CORRECTION LOOP Phase 3 is a Transient Correction Loop that can sum a large amount of current into the output node when required by an out of range condition. The differential feedback summing amplifier is connected directly to the output terminals and has sufficient bandwidth to follow any fast changes in output voltage. The feedback error voltage is compared to the commanded reference voltage (DACOUT) by two high speed comparators, I-Max and I-Min. The other inputs of these comparators are offset from the DACOUT as shown in Fig 6. If the error in output voltage exceeds the offset in either direction the appropriate MOSFET will be turned on to force current into or out of the output node to correct the voltage error. The very low value inductor (100nH) allows large amounts of current to be forced into or out of the output node very quickly. When the Transient Correction Loop is switching it forces the appropriate upper or lower MOSFETs in phases 1 and 2 to stay on (100% or 0% duty cycle) until the error is corrected.
The two drivers for the Transient Correction Loop have outputs (I-Max) and (I-Min) that may be used to drive a half bridge to correct for both low and high output voltage conditions. This permits pulling the output low if an overshoot occurs due to a rapid reduction in load current. With a conventional Buck regulator rapid changes in the negative direction are not possible due to the low voltage available as a forcing function. The two outputs (I-MAX and I-MIN) are completely independent. A single MOSFET and diode can be used to correct for voltage droop only or voltage overshoot only when driven by the appropriate output. If the I-MAX driver is not used the VC3 and VS3 pins must be connected to +5 volts. Under normal operation the Transient Correction phase is only active for a very brief time during high di/dt loads on the output.
DACOUT +5V
VC3 +
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FB -
35mV
I-Max Comparator VCCL
VS3 70nH
FB +
+
35mV
I-Min Comparator
PGN3
Figure 6 - Phase 3 Transient Correction Loop
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
+
I-Max Vout
I-Min
APPLICATIONS APPLICATIONS
Page 12
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
APPLICATION NOTE
OUTPUT INDUCTOR The output inductor should be selected to meet the requirements of the output voltage ripple in steady-state operation and the inductor current slew-rate during transient. The peak-to-peak output voltage ripple is:
VRIPPLE = ESR x I RIPPLE
microprocessor power supply, the output capacitor is usually selected from ESR instead of capacitance or RMS current capability. A capacitor that satisfies the ESR requirements usually has a larger capacitance and current capability than strictly needed The allowed ESR can be found by:
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ESR x I RIPPLE + I < VEX
(
)
where
I = VIN - VOUT L x D fs
I is the inductor ripple current, L is the output inductor value and ESR is the Effective Series Resistance of the output capacitor. I should typically be in the range of 20% to 40% of the maximum output current. Higher inductance results in lower output voltage ripple, allowing slightly higher ESR to satisfy the transient specification. Higher inductance also slows the inductor current slew rate in response to the loadcurrent step change, I, resulting in more output-capacitor voltage droop. When using electrolytic capacitors, the capacitor voltage droop is usually negligible, due to the large capacitance The inductor-current rise and fall times are:
TRISE = Lx I
(V
IN
- VOUT
I
)
and
TFALL = Lx VOUT
Where IRIPPLE is the inductor ripple current, I is the maximum load current step change, and VEX is the allowed output voltage excursion in the transient. Electrolytic capacitors can be used for the output capacitor, but are less stable with age than tantalum capacitors. As they age, their ESR degrades, reducing the system performance and increasing the risk of failure. It is recommended that multiple parallel capacitors be used, so that, as ESR increase with age, overall performance will still meet the processor's requirements. There is frequently strong pressure to use the least expensive components possible, however, this could lead to degraded long-term reliability, especially in the case of filter capacitors. Microsemi's demonstration boards use the CDE Polymer AL-EL (ESRE) filter capacitors, which are aluminum electrolytic, and have demonstrated reliability. The OS-CON series from Sanyo generally provides the very best performance in terms of long term ESR stability and general reliability, but at a substantial cost penalty. The CDE Polymer AL-EL (ESRE) filter series provides excellent ESR performance at a reasonable cost. Beware of off-brand, very low-cost filter capacitors, which have been shown to degrade in both ESR and general electrolytic characteristics over time.
. The inductance value can be calculated by: L= VIN - VOUT I x D fs
INPUT CAPACITOR The input capacitor and the input inductor, if used, are to filter the pulsating current generated by the buck converter to reduce interference to other circuits connected to the same 5V rail. In addition, the input capacitor provides local de-coupling the buck converter. The capacitor should be rated to handle the RMS current requirements. The RMS current is:
I RMS = I L d(0.5 - d) for d < 0.5
APPLICATIONS APPLICATIONS
OUTPUT CAPACITOR The output capacitor is sized to meet ripple and transient performance specifications. Effective Series Resistance (ESR) is a critical parameter. When a step load current occurs, the output voltage will have a step that equals the product of the ESR and the current step, I. In an advanced
Where IL is the inductor current and d is the duty cycle. The maximum RMS value of 0.25IL will occur when d = 25% or 75%.
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 13
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
APPLICATION NOTE (CONTINUED)
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SOFT-START CAPACITOR An external soft-start capacitor is connected to the DACOUT pin and will be charged, or discharged, at a linear rate by the internal 50uA bi-directional current source after the UVLO circuit has been satisfied. Whenever the VID code is changed during normal operation the soft-start capacitor will determine the rate of change at the output.
PROGRAMMING THE OUTPUT VOLTAGE Output voltage is determined by the internal 5 bit DAC. The DAC inputs are the Voltage Identification (VID) 0-4 lines, the VID table lists the available output voltages for the corresponding VID codes. There are no external resistor dividers to program output voltage and only the steps listed are available.
APPLICATIONS APPLICATIONS
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 14
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
PACKAGE DIMENSIONS
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LQ
38-Pin Micro Leadframe Package (MLPQ)
D L
D2
E
E2
3 2 1
e
Dim A A1 A3 b D D2 E E2 e L
A
MILLIMETERS MIN MAX 0.80 1.00 0 0.05 0.20 REF 0.18 0.30 5.00 BSC 3.00 3.25 7.00 BSC 5.00 5.25 0.50 BSC 0.30 0.50
INCHES MIN MAX 0.031 0.039 0 0.002 0.008 REF 0.007 0.011 0.196 BSC 0.118 0.127 0.275 BSC 0.196 0.206 0.019 BSC 0.012 0.020
A1
b
A3
PW
19
38-Pin Thin Small Shrink Outline (TSSOP)
Dim A A1 A2 b c D E E1 e L M *LC MILLIMETERS MIN MAX 1.2 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 9.60 9.80 6.25 6.50 4.30 4.50 0.50 BSC 0.45 0.75 0 8 0.10 INCHES MIN MAX 0.047 0.002 0.006 0.031 0.041 0.007 0.011 0.004 0.008 0.378 0.386 0.246 0.256 0.169 0.177 0.02 BSC 0.018 0.030 0 8 0.004
1
E
20 38
e D A A1 b A2 L c E1 M
MECHANICALS MECHANICALS
Note:
1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006") on any side. Lead dimension shall not include solder coverage.
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 15
LX1677
TM (R)
AMD64 Processor VRM Controller
PRODUCTION DATA SHEET
NOTES
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NOTES NOTES
PRODUCTION DATA - Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time.
Copyright (c) 2000 Rev 1.1, 2003-03-03
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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